The present invention relates, in general, to the field of ferroelectric random access memory devices. More particularly, the present invention relates to a circuit and method for reducing compensation of a ferroelectric capacitor through multiple plate line pulsing following a "write" operation.
Ferroelectric memory devices, such as the FRAM.RTM. family of solid state, random access memory ("RAM") integrated circuits ("ICs") available from Ramtron International Corporation, Colorado Springs, Colo. provide non-volatile data storage through the use of a ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within the Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
A hysteresis curve, wherein the abscissa and ordinate represent the applied voltage and resulting polarization states respectively, may be plotted to represent the response of the polarization of a ferroelectric capacitor to the applied voltage as shown in the solid curve 11 of the attached FIG. 1. A more complete description of this characteristic hysteresis curve is disclosed, for example, in U.S. Pat. Nos. 4,914,627 and 4,888,733 assigned to the assignee of the present invention, the disclosures of which are herein specifically incorporated by this reference.
Data stored in a ferroelectric memory cell is "read" by applying an electric field to the cell capacitor. If the field is applied in a direction to switch the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, sense amplifiers can measure the charge applied to the cell bit lines and produce either a logic "1" or "0" at the IC output pins. In a conventional two transistor/two capacitor ("2T/2C") ferroelectric memory cell, a pair of two data storage elements are utilized, each polarized in opposite directions. To "read" the state of a 2T/2C memory cell, both elements are polarized in the same direction and the sense amps measure the difference between the amount of charge transferred from the cells to a pair of complementary bit lines. In either case, since a "read" to a ferroelectric memory is a destructive operation, the correct data is then restored to the cell during a precharge operation.
In a simple "write" operation, an electric field is applied to the cell capacitor to polarize it to the desired state. Briefly, the conventional write mechanism for a 2T/2C memory cell includes inverting the dipoles on one cell capacitor and holding the electrode, or plate, to a positive potential greater than the coercive voltage shown in FIG. 1 for a nominal 100 nanosecond ("nsec.") time period. The electrode is then brought back to circuit ground for the other cell capacitor to be written for an additional nominal 100 nsec. However, since ferroelectric capacitors tend to become "compensated", (as shown by the dashed curve 13 of FIG. 1, wherein the hysteresis loop appears to shift to favor the stored state due to a charge build-up), such compensation can result in a much lower signal to be presented to the sense amps upon the performance of subsequent "read" operations, thereby possibly indicating a device failure during test.